CapFast /SCAT: Design Concern Analysis (DCA) - Problem Descriptions
Inadequate isolation between tied power sources can cause power bus and power supply failure. Momentary power ties can arise where make-before-break switching is used for selecting power sources. To accommodate power-on and power-off transient conditions, reverse breakdown voltage for isolation devices should be rated for at least the maximum voltage source, not the voltage difference between sources.
Single input power source: Since ground may be disconnected with power still applied, the power source voltage will appear through the circuit impedance at the load side of the ground return and may present a safety hazard to personnel.
Multiple input power sources: Since ground may be disconnected with power still applied, a sneak current path from a higher voltage source to a lower voltage source may exist. In addition, a portion of the power source voltages will appear through the circuit impedance at the load side of the ground return and may represent a safety hazard.
Case 1: Independently Powered Signals
The absolute maximum ratings of certain ICs preclude applying an input signal to the unpowered IC. This is particularly true for CMOS devices due to a latch-up phenomenon.
4. Multiple Power Sources Unintentionally Enabling a Common Load
Case 2: Dual Powered Devices
If power to an IC or vacuum tube device is shut off while input signals remain powered on, the device may be damaged due to voltage breakdown or excessive current.
5. Unintentional Enabling of Power (OR'd Power Switching to Multiple Loads)
This design concern is associated with paralleled, switched power paths connected to paralleled loads in an "X" pattern and leads to a "wired-OR" problem.
6. Ground Potential Difference Between Separated Assemblies
A difference in ground potential between two interfacing assemblies can shift the input signal voltage to the receiving assembly. The voltage shift can distort signal amplification in analog circuitry and lower input noise margins in digital circuitry. Furthermore, if the circuit includes an IC input connected to an off-page connector, then the ground voltage difference also causes IC substrate diodes to become heavily forward biased, thereby damaging the device. This is especially troublesome when the output signal of the driving assembly is in its low state.
7. Unintentional Disabling of Power (AND'd Power Switching to Multiple Loads)
This problem is associated with series switched power paths connected to paralleled loads in an inverted "Y" pattern. The problem arises if a load is unintentionally disabled by one of the switches.
8. Invalid Data Across Separately Powered Digital Interfaces
When the supply voltage is below some threshold during power up or power down, the output of a digital device is unpredictable. During power down, a subsequent device powered from a supply which decays more slowly may therefore receive unpredictable data and produce false results. A similar problem exists for power up.
Where high current switching circuitry shares the same assembly with low power analog or digital circuitry, it is prudent to separate the high and low current ground return paths to avoid excessive electrical noise on the low current ground. Low level analog amplifiers such as IC op-amps or edge triggered devices such as one-shots are particularly sensitive to ground noise.
10. Power Supply and Grounds at Different Reference Levels
The intent of this design concern is to insure connectivity between the ground return at the circuit assembly and the power supply ground node (assuming that the power supply is a physically separate assembly).
11. Mixed High Current and Low Current Grounds
High current loads include displays, motor windings, squibs, and relay coils. Low current loads include logic and low power analog circuitry. By sharing grounds for these two types of loads, voltage transients arising from the resistance and inductance of the high current path can be introduced into the low current circuitry.
12. Indicator Monitoring Relay's Commanded State Rather Than Actual State
The indicator is monitoring the relay coil current rather than the relay contact current. The latter shows the true state of the relay even if it fails to switch.
13. Indicator Monitoring Load Current (Actual State) Rather Than Load Voltage (Commanded State)
If an indicator depends upon the operation of the function it is monitoring, improper or unexpected operation of the function may inhibit the indicator circuitry.
14. Bipolar Junction Transistor Collector Reverse Current
This problem can occur if the collector bias voltage Vcc is removed, possibly as a result of opening a switching device, while a signal is still present at the transistor base.
The summing point of an op-amp adder will remain at virtual ground (if biased at ground) if the op-amp is not saturated. The virtual voltage reference at the "minus" input of an inverting amplifier configuration is maintained only when the amplifier is operating linearly; if the opamp reaches saturation, any additional current into the node at the "minus" input will cause the voltage at the node to rise. The concern is that for a multiple input signal configuration (summing junction), when driven into saturation, a non-zero voltage at the summing point will cause a reverse current to flow into an input signal circuit when that input is at its low state. Saturation also introduces distortion to any analog waveform at the amplifier output.
Only multiple input signal configurations are considered, because single input configurations are likely to have been completely specified and evaluated for all operating conditions (SCA assumes that the circuit performs as specified). This design concern does not consider non-inverting configurations, since the voltage at the "plus" input node is not held at a virtual voltage reference, and current would therefore normally flow from input to input.
16. Relay Coil Suppression Networks (No Diode Across Relay Coil)
A diode network is typically used to suppress voltage transients that arise when a relay coil is de-energized.
17. Relay Coil Suppression Networks (Single Standard Diode w/o Zener in Series Across Relay Coil Terminals)
When coil power is removed, the coil inductance L and the small forward resistance R of the standard diode causes the drop-out time, a function of L/R, to become excessive and may cause a sneak timing problem.
Noise can be capacitively or inductively coupled into a susceptible input from adjacent power lines and switched, high current signal lines. These sneak electromagnetic paths can occur especially when high power devices are mounted on the same circuit board with the susceptible devices.
19. Command Lines Adjacent to Power Lines
Command lines in close physical proximity to power lines are susceptible to power line noise that can cause false triggering or that can mask or delay desired commands.
20. Resistor-Capacitor Networks in Digital Circuits Not Providing the Required Characteristics, Such as Pulse Width and Switching Speed
R-C networks are often used to shape or delay digital signals. For these applications, it is important to account for the output resistance of the digital driver and the input capacitance of the digital receiver(s) in addition to the values of the discrete R-C components when evaluating the resulting pulse width and rise/fall time of the affected signals. The parasitic output and input impedances are particularly relevant for small R-C time constants.
21. Large Resistor-Capacitor Time Constants Causing Excessive Rise or Fall Times in Switching Circuits
A large RC time constant causes an input signal to have slow rise and fall times. Switching times slower than 50 nsec for TTL or 15 usec for MOS can cause multiple false triggering of the device or excessive power dissipation. This occurs when the input signal level dwells in the region between the unambiguous logical 0 and logical 1 states. A Schmitt triggered gate employs positive feedback to virtually eliminate input signal level ambiguity.
A high input capacitance causes input signals to have slow rise and fall times. Switching times slower than 50 nsec for TTL or 15 usec for MOS can cause multiple false triggering of the device or excessive power dissipation.
23. Tapped Line Drivers Feeding On-Board Circuitry
Signal reflections on the transmission line can erroneously trigger logic tied to the driver output.
A negative signal at the input to a digital device can cause faulty operation or damage due to high reverse current flow through the IC substrate. This can occur if the negative signal forward biases the substrate diode. Negative signals can occur on lines receiving data from off the board or on lines coming from circuitry powered by a negative supply.
25. Signals Routed to Unintended Places. Reversal of Polarity or Phase Between Signals
Within a schematic representation of an assembly (e.g., circuit card, control panel, relay/circuit breaker assemblage, etc.), a label of an external input signal (i.e., a signal originating from some other assembly) may have been erroneously transposed such that the character(s) indicating polarity or phase is/are reversed. For example:
-PWR >------> PWR or Q_BAR >------> Q
This is considered a drawing error and should be reported as such.
26. Totem Pole Outputs of Digital Devices Connected Together
The concern addresses digital ICs having totem pole outputs. If two active outputs are wired together, their output stages could be degraded or damaged, or the signal level distorted or held at an indeterminate level, when one is active high and the other active low.
27. Asymmetric Elements or Paths in Circuits Containing Symmetry
The intent of this design concern is to address symmetry/asymmetry within the power and power return distribution circuitry; an asymmetric branch in otherwise symmetrical power and power return circuits is a potential sneak path.
The undesired capacitor discharge paths of concern here are assumed to involve substantial current flow (i.e., a relatively large valued capacitor, assumed to be >= 0.1 uF) and a switching device in series with the path (if the path were not switchable, it is doubtful that the path would be a "latent" sneak).
Examples of undesired effects of discharge paths are:
29. Momentary Undesired Current Paths Present During Change of State of Switching Circuits
The current concern is applicable to cascaded MOS (source-to-drain) or NPN/PNP (collector-to-collector or emitter-to-emitter) transistor configurations where a momentary current path exists during the transition period when one device has turned on before the other has turned off (similar to make-before-break switches).
30. Unintended Modes or False Outputs During Power-Up
The concern typically is applicable to digital circuitry (unintended logic states) in general and to analog circuitry (momentary unintended output levels) requiring multiple power supplies. (Regarding the latter, the assumption is made that turn-on and turn-off transient output levels for analog circuits using a single power supply will have been experienced during normal operation and will not involve "latent" conditions.) If signals such as "power on reset" are present, then the concern possibly is not relevant.
31. Splitting and Then Recombining Digital Signals Sharing a Common Source and Load
Recombined paths often lead to sneak timing problems as a result of the logic functions performed along each path. A specific example of sneak timing caused by unanticipated logic states can be found in NAVSO P3634, Section A.3.5. A more commonly encountered problem is a transient signal ("glitch") caused by differences in the signal propagation delay ("skew") between paths.
32. Noise Margin Limits Exceeded for Digital Devices
For a given logic family, worst case output swings and input thresholds are designed so as to maintain at least a minimum voltage margin to guarantee recognition of the intended logic levels. When logic maximum fan-in or fan-out specifications are exceeded, or when logic families are mixed, or when digital and analog circuitry interface, this voltage margin may not be maintained under worst case conditions. Signal I/O circuitry at an assembly interface are particularly prone to this design concern.
33. Momentary Undesired Current Paths During Change-of-State of Switches
In circuitry containing switching devices, momentary undesired current paths can exist during an intermediate switching state that can arise when two or more switches simultaneously switch. These intermediate states occur due to differences (however small) between switch transition rates.
34. Ground Paths to TTL Device Inputs Which Can Turn the Device On
To avoid falsely triggering or damaging the device, the voltage level at the ground return pin of a TTL device must be more negative than the logical 0 voltage applied to any input pin of the device.
35. Turn-On, Turn-Off, or Open-Close Timing Problems
Typical problems associated with turn-on, turn-off, or open-close timing include transients due to switch contact bounce, slow rise/fall times that exceed operational requirements, and narrow pulse widths that are below operational requirements. These problems are most often encountered at interfaces between analog or electromechanical switching circuits and digital logic. Debounce circuitry and Schmitt triggered input gates can be used to preprocess these signals.
36. Timing Gaps or Overlaps in Switching Circuits
A momentary path between the contacts of a Make-Before-Break switching device can exist during the switching time interval. The path should be analyzed to determine whether they are possible sneak paths.
37. Excessive Skew of a Signal Due to the Capacitance of the Line
Skew, or timing offset, can be caused by signal propagation delay between taps along a single but relatively long bus and can result in a transient output signal ("glitch") where the signals are logically combined. When many IC inputs are distributed along the bus, the cumulative capacitance can cause significant delay. The skew can be reduced by either reducing or equalizing the line capacitance.
38. Undesired Functions Performed by Loads
This is a general concern primarily intended for critical loads (i.e., those whose improper operation could result in mission or safety critical effects). The concern can be analyzed by considering the signals applied to a load for all relevant circuit switching states.
39. Press-to-Test Circuits Energizing Systems
Insure a circuit intended only for test purposes cannot inadvertently energize a system's critical loads.
Switch labels should be compatible with the function performed. For example, "open" and "closed" should not be interchanged for "on" and "off." Consistent nomenclature should be used for designating common switch functions.
41. Labels Not Reflecting True Functions
To avoid ambiguity, manually operated switches should be labeled such that their intended function is understood. For example, a switch intended for opening a door should be labeled "Door Open" rather than "Door," or the switch positions should be labeled "Open" and "Close."