Circuit Extractor
| This tool is a general purpose MOS extractor that operates on a layout file. It extracts a netlist which can be used for simulation, netlist comparison, or electrical rule check. This tool can be used for verification of an entire layout or a single cell. |
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| The Extractor lets you use the evaluation power of
simulation, electrical rules checking, and netlist comparison to
verify your chip layout. It converts mask layout files into netlist files, which the simulators, electrical rules checker, and netlist comparator can use to verify your design. The conversion algorithm is fast and comprehenive, flattening the cell hierarchy throughout the circuit. ACCURATE CIRCUIT MODELING The netlist produced by the Circuit Extractor describes the extracted circuit in terms of the dimensions of the transistors and nodes in the circuit. The simulator programs then use these values to calculate the "on" resistance of each transistor and the capacitance of each node. The resulting electrical model allows you to simulate the operation of your circuit more accurately. The electrical rules checker uses this size data to check for design inconsistencies such as unusually configured transistors, pullup/pulldown ratio errors, or threshold voltage errors. The netlist comparator uses the size data to compare one layout with another or to compare the netlist for a mask layout with the netlist for a schematic diagram netlist. NODE NAME AND ALIAS FILES Along with the netlist file, the Circuit Extractor also produces a node name file and an alias file. As part of the circuit extraction process, the extractor assigns names to any nodes that have not been previously named and resolves any conflicts between nodes that are given different names at different levels of the cell hierarchy. The node name file provides you with a comprehensive list of the node names that the extractor either assigned or selected. You can then display this file with the layout editor in order to identify and locate the nodes in which you are interested in the physical layout. An alias name file lists the nodes where name conflicts occurred and shows how the extractor resolved the conflict. The simulators read this file, allowing you to use any of the node names from any level of the layout hierarchy to specify a node. |
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